Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional ADC. ADC 100 generally comprises a track-and-hold (T/H) circuit 102 and a sub-ADC 104 so that, in operation, the ADC 100 can sample an analog input signal X(t) at a plurality of sampling instants and convert the sampled signal into a digital signal Y[n]. As is shown in FIG. 1, though, the T/H circuit 104 generally comprises switches and capacitors. The switch has a non-zero resistance, which causes the T/H circuit 102 to function as a filter (typically a single pole low pass filter).
Turning to FIG. 2, a model 200 of the ADC 100 is shown. In model 200, the filter aspects of the ADC 100 are represented by filter 202, while the remainder of the functionality of the ADC 100 is represented by ideal ADC 204. Filter 202 has a transfer function in the time-domain of ha (t), which can, in turn, be represented in the frequency-domain as:
                                                        H              a                        ⁡                          (              ω              )                                =                                                    g                a                            ⁢                              ⅇ                                  ⅈ                  ⁢                                                                          ⁢                  ωΔ                  ⁢                                                                          ⁢                  t                                                                    1              +                              ⅈ                ⁡                                  (                                      ω                                          ω                      a                                                        )                                                                    ,                            (        1        )            where ga is the gain of ADC 100, Δta is the time delay relative to a reference, and ωa is the cutoff frequency (bandwidth). This model 200 can be useful when determining mismatches for TI ADCs.
In FIG. 3A, an example of a TI ADC 300 can be seen. TI ADC 300 generally comprises ADCs 100-1 to 100-M (where each of ADCs 100-1 to 100-M generally has the same structure as ADC 100 from FIG. 1) that are clocked by divider 302 so that the outputs from ADCs 100-1 to 100-M can be multiplexed by multiplexer 304 to produce digital signal Y[n]. Yet, when building TI ADC 300, ADCs 100-1 to 100-M are not identical to each other; there are slight structural and operational variations. These slight variations result in Direct Current (DC) offset mismatches, timing skew, gain mismatches, and bandwidth mismatches between ADCs 100-1 to 100-M.
Of the different types of mismatches listed, the performance impact, as the result of bandwidth mismatches, are the weakest, and, to date, have largely been ignored, but, in order to build a high accuracy (generally greater than 6 bits), high speed (generally greater than 1 GS/s) TI ADCs, bandwidth mismatches between interleaved ADC branches need to be corrected. Looking to TI ADC 300, the output spectrum when the input signal is a tone with frequency ω* can be represented as follows:
                              Y          ⁡                      (                          ⅇ              ⅈω                        )                          =                              ∑                          k              =              0                                      M              -              1                                ⁢                                    (                                                1                  M                                ⁢                                                      ∑                                          a                      =                      0                                                              M                      -                      1                                                        ⁢                                                                                    H                        a                                            ⁡                                              (                                                  ω                          *                                                )                                                              ⁢                                          ⅇ                                                                        -                          ⅈ                                                ⁢                                                                              2                            ⁢                            π                            ⁢                                                                                                                  ⁢                            k                                                    M                                                ⁢                        a                                                                                                        )                        ⁢                                          δ                ⁡                                  (                                      ω                    -                                          ω                      *                                        -                                                                  2                        ⁢                        π                        ⁢                                                                                                  ⁢                        k                                            M                                                        )                                            .                                                          (        2        )            Assuming a 2-way TI ADC (M=2), which generally represents the upper-bound or worst-case for bandwidth mismatch, equation (2) can be reduced to:
                              Y          ⁡                      (                          ⅇ              ⅈω                        )                          =                                            (                                                                                          H                      0                                        ⁡                                          (                                              ω                        0                                            )                                                        +                                                            H                      1                                        ⁡                                          (                                              ω                        0                                            )                                                                      2                            )                        ⁢                          X              ⁡                              (                                  ⅇ                  ⅈω                                )                                              +                                    (                                                                                          H                      0                                        ⁡                                          (                                              ω                        0                                            )                                                        +                                                            H                      1                                        ⁡                                          (                                              ω                        0                                            )                                                                      2                            )                        ⁢                          X              ⁡                              (                                  ⅇ                                      ⅈ                    ⁡                                          (                                              ω                        -                        π                                            )                                                                      )                                                                        (        3        )            with a Spurious-Free Dynamic Range (SFDR) of
                    SFDR        =                  20          ⁢                                          ⁢                                    log              10                        ⁡                          (                                                                                          H                      0                                        ⁡                                          (                                              ω                        0                                            )                                                        +                                                            H                      1                                        ⁡                                          (                                              ω                        0                                            )                                                                                                                                  H                      0                                        ⁡                                          (                                              ω                        0                                            )                                                        -                                                            H                      1                                        ⁡                                          (                                              ω                        0                                            )                                                                                  )                                                          (        4        )            The SFDR for an M-way interleaved TI ADC, therefore, can then be determined to be:
                              SFDR          =                                    max              k                        ⁢                          (                              20                ⁢                                                                  ⁢                                                      log                    10                                    ⁡                                      (                                                                  A                        ⁡                                                  [                          0                          ]                                                                                            A                        ⁡                                                  [                          k                          ]                                                                                      )                                                              )                                      ⁢                                  ⁢        where                            (        5        )                                          A          ⁡                      [            k            ]                          =                              ∑                          a              =              0                                      M              -              1                                ⁢                                                    H                a                            ⁡                              (                                  ω                  0                                )                                      ⁢                          ⅇ                                                -                  ⅈ                                ⁢                                                      2                    ⁢                    π                    ⁢                                                                                  ⁢                    k                                    M                                ⁢                a                                                                        (        6        )            Now, equation (1) can be applied to TI ADC 300 for the purposes of simulation so
                                                        H              a                        ⁡                          (                              ω                0                            )                                =                      1                          1              +                              ⅈ                ⁢                                                                  ⁢                                  τ                  a                                ⁢                                  ω                  0                                                                    ,                                  ⁢                                            for              ⁢                                                          ⁢                              T                S                                      >                          τ              a                                =                      1                          ω              a                                      ,                            (        7        )            where TS is the period of clock signal CLK. Such a simulation yields that variations in bandwidth mismatches are dependent on gain mismatches and timing skews and that (with high accuracy, high speed TI ADCs) bandwidth mismatch can significantly affect performance. An example of a simulation of the effect bandwidth mismatch can be seen in FIG. 3B for different gain and skew compensations. Thus, to achieve the desired SFDR (i.e., greater than 70 dB) for a TI ADC, the bandwidths of ADCs within the TI ADC should be matched to be within 0.1% to 0.25%.
To date, however, no estimation algorithm or circuit exists to blindly determine bandwidth mismatches. The two most relevant conventional circuits, though, are described in the following: Satarzadeh et al., “Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter,” Proceedings of 2007 IEEE International Symposium on Circuits and Systems, 2007; and Tsai et al., “Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 53, No. 10, pp. 1133-1137, Oct. 23, 2006. Neither of these circuits, though, adequately addresses blind bandwidth mismatch estimation.
Assuming, however, that one is able to adequately perform blind bandwidth mismatch estimation, adjustment of bandwidths of the T/H circuits (like T/H circuit 102) in TI ADC 300 can be difficult due at least in part to the precision of the bandwidth matching. A switched capacitor arrangement included within the T/H circuit 102 would be undesirable because it would be difficult to implement, and capacitive tuning (such as with a varactor and a tuning voltage) would also be undesirable because of signal dependencies. Thus, there is a need for a bandwidth adjustment circuit that can be adjusted from a blind bandwidth mismatch estimation.
Some other conventional circuits are: U.S. Pat. No. 5,500,612; U.S. Pat. No. 6,232,804; U.S. Pat. No. 6,255,865; U.S. Patent Pre-Grant Publ. No. 2004/0070439; U.S. Patent Pre-Grant Publ. No. 2004/0239545; U.S. Patent Pre-Grant Publ. No. 2009/0009219; and Abo et al. “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. of Solid State Circuits, Vol. 34, No. 5, pp. 599-606, May 1999;